A DRAM is a memory element which holds and supplies information for use by electronic digital computing and logic elements, such as microcontrollers, microprocessors, logic arrays, and the like. An ASIC or an SLIC is a single IC which includes a combination of various electronic components, such as microcontrollers, microprocessors, logic gates, registers, amplifiers, linear circuit elements and the like, all of which have been selected, connected and integrated together to perform specific functions for a specific application. Examples of SLICs are controllers for computer memory disc drives, graphics controllers, LAN switches, fuel injector control systems for internal combustion engines, global positioning systems, and control devices for a wide variety of consumer products, among many others. SLICs are desirable for use in mass-produced products because of the enormous amount of functionality which can be obtained at a very low effective cost. These types of SLICs are sometimes referred to as a "system on a chip," because of the complete functionality obtained from the single chip or IC.
DRAMs have only recently been "embedded" or incorporated as part of SLICs. Previously, when the SLIC required memory to function, separate memories or DRAM chips were provided on a printed circuit board. Embedding DRAM in a SLIC chip avoids the additional cost of a separate memory chip. Avoiding the cost of the separate DRAM chip is attractive when the SLIC itself requires only a small amount of memory, because separate DRAM chips are relatively costly and of considerable memory size. Even when more substantial amounts of memory are required, the incorporation of the memory in the single SLIC chip will frequently be less expensive than purchasing a separate DRAM chip.
The typical DRAM is formed by thousands of individual memory cells arranged in a matrix-like configuration and formed into a substrate of the SLIC. Each DRAM cell includes a capacitor which is electrically charged or discharged in a "write" operation. The charge establishes a voltage on the capacitor, and the level of the voltage represents a data bit. The data bit represented by the capacitor charge is determined by comparing the capacitor voltage to a threshold reference. The voltage levels which must be sensed to establish the data bit level of the cell in a DRAM are relatively small, e.g. 50-100 millivolts, and differences in signals of less than 50 millivolts may mean the difference between an accurate or an inadequate data bit determination.
The memory cells of the DRAM matrix are addressed by signals supplied on word lines and bit lines. The word lines extend in a horizontal reference direction in the matrix and connect to the memory cells in the horizontal rows and thus intersect vertical columns of memory cells in the matrix. The bit lines extend in a vertical reference direction in the matrix and connect to the memory cells in vertical columns and thus intersect horizontal rows of cells. By energizing a selected word line, the voltage from the memory cells in the horizontal row corresponding to the selected word line are presented on the bit lines extending from each of the cells.
The DRAM memory array is usually divided into one or more segments, and each of the segments is further divided into bit blocks. Each bit block has a plurality of memory cells, and those memory cells are organized into rows and columns in a matrix. Individual words are selected by addressing the DRAM segments, selecting individual columns in the bit blocks, and selecting the desired word line.
One disadvantage associated with embedding the DRAM in the SLIC is that the noise from the other logic components of the SLIC may cause the performance of the DRAM to decline. The other logic and integrated circuit components continuously switch between conductive and nonconductive states and cause current to begin and end flowing within these circuit components, the conductors throughout the SLIC, the substrate of the SLIC, lead bonds connecting the SLIC chip to external components, and external components themselves. Generally, when current flow stops quickly, the electrical inductance of the associated circuit elements causes a voltage spike or pulse to ripple through the circuit components on the SLIC substrate. The voltage pulse may be sufficient to cause the voltage on the substrate to fluctuate or "bounce." Voltage bounces may reach as high as 1 volt and may be of enough magnitude to corrupt the bit line signals and data stored in some of the memory cells. Furthermore, once the memory cell capacitors discharge onto the bit lines, the typical voltages on bit lines are much smaller than the voltages present on the memory cell capacitors because of the larger capacitance of the bit lines compared to the memory cell capacitors. Typical bit line voltages are in the range of tens or hundreds of millivolts while typical memory cell capacitor voltages are in the range of 1 to 3 volts. With such low bit line voltages, a substrate which is subject to relatively large voltage bounces often makes it impossible or difficult to sense the bit line voltages accurately.
Noise influences on the DRAM can also originate because of a connection between the SLIC and the electronic devices external to the SLIC on the printed circuit board, particularly when the external devices draw a large amount of current. Current transients conducted through the lead bonds and other conductors may create voltage pulses, because of the inductance of the current conducting elements. For example, an external data bus is typically connected to the SLIC over which to read data bit signals. A read process may draw a large amount of current in very short amount of time. The resulting current surge creates a voltage pulse, and that voltage pulse may adversely impact the performance of the DRAM.
To avoid noise problems, several approaches have been explored. One approach involves attempting to determine when the noise will occur and then reading the DRAM only during quiet times. Since most of the operations in simple systems are controlled by clock pulses, it is possible to predict when some functional operations will take place and generate noise. However, this approach is impractical in most complex SLICs because multiple clocks are used to control the different components of the SLIC. Determining when the noise will occur on a consistent basis requires that the multiple clocks be synchronized, which is difficult, impossible or impractical. Further, given the many operations that the SLIC performs on a continuous basis, quiet times may not exist for long enough periods of time to enable satisfactory DRAM operation.
Another approach to avoiding noise problems is to attempt to find a location on the SLIC substrate for the DRAM which is substantially free from noise. However, noise-immune locations are non-existant in many SLICs. The location of the DRAM portion of the SLIC varies from one SLIC chip to the next, because each SLIC chip is generally different from others in configuration and in lay-out. Each SLIC is for a different specific application and uses different elements to accomplish that different function. Thus, a quiet location on one SLIC chip may not be a quiet location on another SLIC chip.
Another approach to reducing the impact of noise on the DRAM has been to use biasing techniques. Since the voltage of each memory cell must be compared to a threshold voltage to determine whether the data bit is high or low, by adjusting or biasing the threshold voltage, some noise-induced variance in the sensed voltages can be accommodated. However, the noise from large voltage bounces on the substrate may be so large in comparison to the bit line voltages that biasing cannot avoid the noise. Often, the entire substrate is biased to reduce the effect of noise caused by the voltage bounces. The substrate is typically connected to the negative power supply. By making the substrate more negative in voltage, the voltage fluctuations may have a reduced effect on the data signals stored in the memory. Substrate voltage bounces usually result in an uneven voltage distribution and differential across the substrate. The uneven distribution affects the signals on the bit lines to differing degrees depending upon the location of the bit lines relative to the location of the voltage differential in the substrate. Under such circumstances, biasing the entire substrate does not compensate for the differential. For these and other reasons, the unique noise environment of each SLIC, the differing physical locations of the DRAM on the SLIC chip, and the differing external components to which the SLIC chip may be connected, generally combine to make biasing techniques ineffective in solving noise problems.
Another cause of data corruption in a DRAM is alpha particles. Alpha particles are high energy cosmic rays which are naturally present to a small degree in the environment. The alpha particles occasionally pass through the substrate of the SLIC and generate a small cloud or wake of positive and negative charge carriers (holes and electrons, respectively). Some of these charged carriers may combine with the charges in the memory cell capacitor and discharge the capacitor, thereby corrupting the data stored in the cell. This condition creates a so-called "soft error," since the cell has not been permanently damaged but has only lost its stored data due to the influence of the alpha particles.
It is with respect to these and other considerations relating to noise in DRAM embedded in SLICs that the present invention has evolved.